1. Field of the Invention
This invention relates to methods of manufacturing semiconductor devices, and more particularly to methods of manufacturing dynamic memory devices using vertical-metal oxide semiconductor (V-MOS) technology.
2. Description of the Prior Art
In the art of manufacturing semiconductor products the cost of production is inversely related to the number of devices which can be placed on a single semiconductor chip and directly related to the number and complexity of manufacturing process steps necessary to fabricate the product.
Until recently, efforts to increase device component density have been limited by minimum photolithographic dimensions previously achievable in the industry. Recently, however, techniques have become available which enable dimensions of less than one micron to be used in photolithographic processing. Although this enables higher density components to be defined per se, actual component densities can not be substantially increased due to device size requirements dictated by required electrical characteristics. In order to provide further density improvement, interest has recently turned to vertical integration techniques which enable physical devices of predetermined size to utilize less planar surface area of semiconductor chips, thus effectively increasing device density. For example, the article, "Grooves add new dimension to V-MOS structure and performance," by F. B. Jenne, Electronics, Aug. 18, 1977, pp. 100-106, discusses some aspects of V-MOS technology and illustrates several techniques for increasing effective device density through the use of V-MOS technology.
Although increases in effective device density through the use of vertically integrated structures helps to reduce the cost of products produced, significant additional cost reduction may also be had by minimizing the number and complexity of manufacturing process steps. This is particularly true when the number of critical mask alignment steps are reduced, since improved density is also provided. Thus, manufacturing processes which include a high number of self-aligning steps, i.e., process steps which do not require the alignment and associated tolerance of photolithographic masks, can directly influence cost of production.
Prior art techniques which use vertical processing techniques in combination with self-aligning masking steps include the following references.
The article, "VMOS ROM," by T. J. Rodgers et al., IEEE J. Solid State Circuits, Vol. SC-11, No. 5, Oct. 1976, pp. 614-622, teaches a self-aligning diffusion technique for ensuring the continuity of a diffused device interconnecting line as it passes a V-groove etched MOSFET. An oxide masking layer is used to first define a localized diffusion and then to define the V-groove.
U.S. Pat. No. 4,116,720 to Vinson uses a similar technique to define both a V-groove and an ion-implanted storage node for a dynamic memory cell.
Copending U.S. patent application, "Method for Providing Self-Aligned Conductor in a V-groove Device," R. R. Garnache et al., Ser. No. 103,981, filed Dec. 17, 1979, now U.S. Pat. No. 4,295,924, teaches a method for forming self-aligned electrodes in V-MOS technology.
U.S. Pat. No. 3,924,265 to Rodgers is of interest as it describes several processing alternatives useful in fabricating devices in V-MOS technology.
U.S. Pat. No. 4,003,036 to Jenne describes a single FET/capacitor dynamic memory cell of the type to which the preferred embodiment of the invention described here has been applied.
Additional references related to techniques useful in practicing the subject invention include:
U.S. Pat. No. 4,095,251 to Dennard et al. which relates to single FET/capacitor memory cells including self-aligned gate electrode to word line conductor contacts in which a non-oxidizing protective masking layer such as silicon nitride is used to form a self-aligned contact between a polysilicon electrode and a metal conductor.
U.S. Pat. No. 3,653,898 to Shaw is representative of a number of references which teach the use of intersecting multiple mask images in order to form one or more apertures in a masking layer in order to form various portions of a semiconductor device, and
U.S. Pat. No. 3,390,025 to Strieter teaches the use of a similar multiple mask etching technique to make multiple contacts to a single semiconductor device.